PhD Ferroelectric Transistors (FeFET) Aware Logic Synthesis

In the digital circuits production flow, the Synthesis takes in input the circuit model description, usually expressed in a hardware description language (e.g., VHDL, Verilog) and produces as output the gate level netlist for a given layout floorplan. The Synthesis flow is mainly composed of two main steps: (i) Logic synthesis and optimization and (ii) Place&Route.

As defined in [1], the overall problem of logic synthesis is the one of finding ``the best implementation'' of a Boolean function. The term ``best'' corresponds to a trade-off between several metrics such as the area, delay, and power consumption. The Place&Route aims at optimizing the physical placement of each logic gate into a given layout floorplan and route the logic gate interconnections. It is important to keep in mind that logic synthesis is usually based on the knowledge of the technology used to implement logic gates and consists of mapping Boolean functions into the ``Best'' interconnection of instances of library elements.

Today, with the rising of alternative technologies to CMOS, we are facing new challenges for logic synthesis. It is therefore mandatory to well understand the logic and sequential gates built on the top of emerging technologies and identify the available opportunities. This thesis will focus on the ferroelectric transistor (FeFET) that is simply an extension of a regular bulk or FDSOI (Fully Depleted Silicon On Insulator) MOSFET with an additional layer of ferroelectric HfO2-based material [2] inside the gate stack.

The ferroelectric layer behaves as a ferroelectric capacitance which actually controls the state of the FET channel. FeFETs operate in two different modes: a non-volatile mode, which requires hysteretic operation, and a steep switching mode, which can be hysteretic or non-hysteretic [2]. The ratio between the ferroelectric capacitance and the dielectric capacitance determines the FeFET operation mode.

This thesis aims at studying Both n- and p-type FeFET transistors based on real physical devices [2]. The first goal is to design a technological library further used for the Logic Synthesis and FeFET memory elements design. The second goal is to investigate existing logic synthesis tools (such as ABC [3]) and adapt them to work with the FeFET technology.

This thesis falls in the framework of the French-German research project HiLoDa Nets, the Electronic group at INL will work in collaboration with the Hardware/Software Co-Design of the Department of Computer Science at the FriedrichAlexander- Universität Erlangen-Nürnberg (FAU). In this context we are currently looking for a (m/f) PhD student for a 3-year contract to be supervised by Damien Deleruyelle (INL) and Cédric Marchand (INL).

Job description

The Ph.D. thesis is structured in the following 5 main tasks

1. FeFET Modeling (M1 to M6)

• In this task, the FeCap compact model available at INL will be used to build n and p-type FeFET unit cells. The Verilog-A FeCap model will be integrated into Spectre and coupled to n- and p-MOSFET models available from standard 28 nm design kits to build the corresponding n- and p-type FeFET unit cells. The models will be calibrated from data collected at INL on HZO FeCap, at NaMLab in the context of the existing collaboration with INL and if still needed refined on available data on FeFET/FeMFET from the literature. As an outcome, this task will deliver n- and p-type FeFET unit cells with calibrated model cards accounting for realistic programming voltages and timing dependencies of the ferroelectric NV elements.

2. Design of logic/sequential Elements with Mixed Volatile/Non-volatile Mode (M6 to M12)

• This task will start from the state-of-the-art with sequential elements as described in [2]. Our idea is to investigate the use of a simpler 1T-1C structure to implement a non-volatile memory element because this will lead to smaller area footprints. Similar approach will be applied to the design and characterization of logic gates (i.e., NAND, XOR, NOT, …).

3. Characterization of FeFET-based Logic/Memory Elements (M13-M18)

• The goal of this task is to characterize different logic/memory elements previously designed. Each element will be characterized in terms of propagation, read/write and backup/recovery times, energy, and endurance. The characterization will be done through Spice simulations (using the transistor-level models and the n- and p-type FeFET models). The characterization results will be used to compile the technological library (i.e., the .lib file) to be used by logic synthesis tools.

4. FeFET aware logic synthesis (M18 – M28)

• This task aims at analyzing the state of the art of synthesis tools and methodologies. It will start from well-known open-source solutions such as ABC [3]. The first goal is to evaluate the actual version of the tool when using the FeFET technology library. The second goal will be to extend ABC to optimize the synthesis for the FeFET technology. 5. Evaluation and Dissemintation (M6-M36)

• Evaluation will be done through simulation and potentially ASIC demonstrators in collaboration with NAMLAB; • Scientific papers and thesis manuscript preparation.
 

About INL

INL is a 250-strong research institute based in Lyon, France, carrying out fundamental and applied research in electronics, semiconductor materials, photonics and biotechnologies. The Electronic group is a leader in the area of advanced nanoelectronic design, with research projects and collaborations at both national and European level. Recent highlights include the modelling of emerging technologies for digital circuits design [4,5]. 

References: [1] E. Testa, M. Soeken, L. G. Amar, and G. D. Micheli, “Logic synthesis for established and emerging computing,” Proceedings of the IEEE,vol. 107, pp. 165–184, Jan. 2019. [2] I. O’Connor, et al., “Prospects for energy-efficient edgecomputing with integrated HfO2-based ferroelectric devices,” in 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 180–183, 2018. [3] Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/. [4] A. Bosio et al. “Emerging Technologies: Challenges and Opportunities for Logic Synthesis.” In DDECS, 2021. [5] C. Maneux et al. “Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence.” In: IEDM, 2021.