Job Information
- Organisation/Company
- INESC ID
- Research Field
- Engineering » Computer engineering
- Researcher Profile
- First Stage Researcher (R1)
- Country
- Portugal
- Application Deadline
- Type of Contract
- Other
- Job Status
- Other
- Is the job funded through the EU Research Framework Programme?
- Not funded by an EU programme
- Reference Number
- AINUR – Refª PTDC/CCI-COM/4485/2021 - BI|2024/515 and 516
- Is the Job related to staff position within a Research Infrastructure?
- No
Offer Description
Public notice for research grant
Project AINUR – Refª PTDC/CCI-COM/4485/2021
BI|2024/515 - BI|2024/516
INESC-ID - Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa is a R&D institute dedicated to advanced research and development in the fields of Information Technologies, Electronics, Communications, and Energy. INESC-ID has participated in more than 50 research projects funded by the European Union and more than 190 funded by national entities. Until today, our researchers have published more than 700 papers in international journal papers, more than 3000 papers in international conferences, and have registered 15 patents and/or brands.
1 | RESEARCH GRANT TYPE
TWO (2) research grants for candidates with BSc degree with reference number BI|2024/515 andBI|2024/516 are now available under the scope of project AINUR, with theRefª PTDC/CCI-COM/4485/2021 , funded byfundação para a ciência e a tecnologia i.p., and under the following conditions:
2 | DURATION
SIX (6) months, starting in April 2024
- Renewable, if the candidate is enrolled in a MSc program - art. 6º, n.4 b)
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
subject to suitable performance within the period of the project, not exceeding the maximum period set by FCT for such grants – 2 years (included contract renewals)
- Renewable, if the candidate is enrolled in a non-degree programme – art. 6º, n. 4 a)
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
subject to suitable performance within the period of the project, not exceeding the maximum period set by FCT for such grants – 1 year (included contract renewals)
3 | LEGISLATION
A fellowship contract will be celebrated according to:
- Law 40/2004 of 18th of August (Scientific Research Fellow Status) and its successive amendments, including the amendments introduced by the Decree Law n. 123/2019 of 28 th of August
https://dre.pt/web/guest/legislacao-consolidada/-/lc/124281176/201912061112/73740605/diploma/indice?lcq=estatuto+do+bolseiro,
- Regulations for Research Grants of the Foundation for Science and Technology in force
https://www.fct.pt/financiamento/programas-de-financiamento/bolsas/
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
https://dre.pt/dre/legislacao-consolidada/lei/2004-58216179
- INESC-ID Lisboa Grant Regulations
https://www.inesc-id.pt/scholarship-regulations/
The fellowship contract is awarded on an exclusive dedication basis – art. 5 of Scientific Research Fellow Status and art. 16 of Regulations for Research Grants of the Foundation for Science and Technology.
4 | MONTHLY AMOUNT
The monthly amount of the grant 990,98€ is in accordance with the values stipulated in the “Regulations for Research Grants of the Foundation for Science and Technology” in force https://www.fct.pt/wp-content/uploads/2024/02/Tabela-de-Valores-SMM_atualizacao-2024.pdf and shall be rendered through a monthly bank transfer to an account held by the grantee.
5 | OBJECTIVES/WORKPLAN
BI|2024/515
The goal of this work is to redesign SPHT (the state-of-the-art solution for persistent memory transactions relying on the previous version of Intel TSX, proposed by our team at INESC-ID) to take into account two technological trends: (1) the opportunity of the new transactional instructions that are now available in the latest generations of Intel CPUs (Sapphire Rapids and Emerald Rapids); (2) the restriction that Intel Optane Persistent Memory has been discontinued, so that the new systems must either resort to fast PCIe-based SSD storage or, in the future, to CXL-based persistent memories.
The proposed solution is expected to ensure crash consistency guarantees, will also be tested using the tools developed by the Ainur project.
The work plan will include:
a) Design a new algorithm for persistent hardware transactions for the above-mentioned trends, borrowing ideas from SPHT.
b) Implement and evaluate the new system, using realistic workloads from relevant benchmarks and focusing on the two possible scenarios for the persistent memory (SSD and CXL).
c) Test the proposed solution using tools from the Ainur project.
The expected outcome is a design and implementation of the above-mentioned system, together with a comprehensive experimental evaluation, to be presented in at least one scientific paper.
BI|2024/516
The goal of this work is to study the synchronization mechanisms that eBPF provides to programs that need to concurrently access data structures maintained in shared memory, and to propose improved mechanisms that exploit more sophisticated techniques from literature – including wait-free data structures and hardware transactional memory.
Complementarily, we will consider eBPF programs that store the shared data structures durably on persistent memory.
This work will mainly focus on highly concurrent eBPF workloads, for which synchronization is a major challenge.
The work plan will include:
a) Experimentally study the performance and progress trade-offs of the existing synchronisation support of eBPF, which is based on spin locks.
b) Design, implement and evaluate at least one alternative synchronization mechanism for eBPF. The evaluation will use realistic high-contention workloads from relevant eBPF benchmarks and publicly available eBPF programs. Furthemore, the evaluation should also consider scenarios where the shared data structures are maintained persistently in persistent memory (such as Intel Optane DC PM).
The expected outcome is a design and implementation of the above-mentioned system, together with a comprehensive experimental evaluation, to be presented in at least one scientific paper.
6 | SCIENTIFIC SUPERVISION
The activities will be supervised by João Pedro Faria Mendonça Barreto, Associate Professor at Instituto Superior Técnico and Researcher at INESC-ID.
INESC ID will integrate the grantees in the research team of the scientific advisor.
7 | ADMISSION REQUIREMENTS
The candidates should have a BSc in Computer Engineering, or related areas.
By the grant start date, the candidates must be enrolled in :
- a MSc programme – art. 6º, n.1
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
or
- a non-degree programme – art. 6º, n. 2
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
Preferential factors:
- proficiency in Portuguese
- proficiency in English
8 | EVALUATION CRITERIA AND COMMITTEE
The selection will be according to the following criteria:
1 - Academic record (50%)
2 - Experience in the domain of operating systems (50%)
The jury may also decide not to assign the scholarship, if none of candidates meets the required conditions.
Jury | Name | Professional Status | Institutions |
President | Paolo Romano | Researcher / Associate Professor | INESC-ID / IST |
Member | Miguel Ângelo Marques de Matos | Researcher / Assistant Professor | INESC-ID / IST |
Member | João Pedro Faria Mendonça Barreto | Researcher / Assis Associate | INESC-ID / IST |
Substitute member | Miguel Filipe Leitão Pardal | Researcher / Assistant Professor | INESC-ID / IST |
Substitute member | João Coelho Garcia | Researcher / Assistant Professor | INESC-ID / IST |
9 | COMPLAIN AND APPEAL DEADLINES AND PROCEDURES
The jury has the faculty not to select a candidate who does not prove the requirements mentioned in required education Level and research experience
The admitted and excluded candidates will be notified by email of the final ranking list, including the copy of the Preliminary Report of the jury.
Prior Hearing and Deadline for Final Decision: After being notified, candidates have 10 working days to submit, if applicable, a formal rebuttal.
After that period, the jury notifies the candidates of the Final Report.
Excluded applicants may complain about the jury's final report for 15 working days after notification or appeal the jury's decision to the INESC ID Board of Directors for 30 working days after notification.
According to the Portuguese Law, a disabled candidate has a preference when in equal classification, which prevails over any other legal preference. Candidates must declare their respective degree of disability, the type of disability and the means of communication / expression to be used in the selection process, under the law.
10 | FORMALISATION OF APPLICATIONS
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10.1 | Single copy of official academic degree certificate in the required education level |
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a) In the application submission, the candidates from portuguese education institutions may replace the copy of official academic degree certificate by a declaration of honour stating that they have the required academic degree. |
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| b) In the application submission, the candidates from foreigner education institutions may replace the copy of official academic degree certificate by a declaration of honour stating that they have the required academic degree. |
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10.2 | Detailed list of grades (pdf form); |
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10.3 | Proof of enrolment required on 7 a) or 7 b) (pdf form); |
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In the application submission, the candidates may replace the proof of enrolment by a declaration of honour stating that they are/will be enrolled required in 7 a) or 7 b) |
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10.4 | Detailed curriculum vitae (pdf form); |
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10.5 | Motivation letter explaining the interest in the position (pdf form); |
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11 | Application Dates
From |
| To |
15-03-2024 |
| 28-03-2024 |
Requirements
- Research Field
- Engineering » Computer engineering
- Education Level
- Bachelor Degree or equivalent
BI|2024/515
The goal of this work is to redesign SPHT (the state-of-the-art solution for persistent memory transactions relying on the previous version of Intel TSX, proposed by our team at INESC-ID) to take into account two technological trends: (1) the opportunity of the new transactional instructions that are now available in the latest generations of Intel CPUs (Sapphire Rapids and Emerald Rapids); (2) the restriction that Intel Optane Persistent Memory has been discontinued, so that the new systems must either resort to fast PCIe-based SSD storage or, in the future, to CXL-based persistent memories.
The proposed solution is expected to ensure crash consistency guarantees, will also be tested using the tools developed by the Ainur project.
The work plan will include:
a) Design a new algorithm for persistent hardware transactions for the above-mentioned trends, borrowing ideas from SPHT.
b) Implement and evaluate the new system, using realistic workloads from relevant benchmarks and focusing on the two possible scenarios for the persistent memory (SSD and CXL).
c) Test the proposed solution using tools from the Ainur project.
The expected outcome is a design and implementation of the above-mentioned system, together with a comprehensive experimental evaluation, to be presented in at least one scientific paper.
BI|2024/516
The goal of this work is to study the synchronization mechanisms that eBPF provides to programs that need to concurrently access data structures maintained in shared memory, and to propose improved mechanisms that exploit more sophisticated techniques from literature – including wait-free data structures and hardware transactional memory.
Complementarily, we will consider eBPF programs that store the shared data structures durably on persistent memory.
This work will mainly focus on highly concurrent eBPF workloads, for which synchronization is a major challenge.
The work plan will include:
a) Experimentally study the performance and progress trade-offs of the existing synchronisation support of eBPF, which is based on spin locks.
b) Design, implement and evaluate at least one alternative synchronization mechanism for eBPF. The evaluation will use realistic high-contention workloads from relevant eBPF benchmarks and publicly available eBPF programs. Furthemore, the evaluation should also consider scenarios where the shared data structures are maintained persistently in persistent memory (such as Intel Optane DC PM).
The expected outcome is a design and implementation of the above-mentioned system, together with a comprehensive experimental evaluation, to be presented in at least one scientific paper.
The candidates should have a BSc in Computer Engineering, or related areas.
By the grant start date, the candidates must be enrolled in :
- a MSc programme – art. 6º, n.1
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
or
- a non-degree programme – art. 6º, n. 2
- Languages
- ENGLISH
- Level
- Good
- Languages
- PORTUGUESE
- Level
- Good
Additional Information
The monthly amount of the grant 990,98€ is in accordance with the values stipulated in the “Regulations for Research Grants of the Foundation for Science and Technology” in force https://www.fct.pt/wp-content/uploads/2024/02/Tabela-de-Valores-SMM_atualizacao-2024.pdf and shall be rendered through a monthly bank transfer to an account held by the grantee.
The candidates should have a BSc in Computer Engineering, or related areas.
By the grant start date, the candidates must be enrolled in :
- a MSc programme – art. 6º, n.1
https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf
or
- a non-degree programme – art. 6º, n. 2
The selection will be according to the following criteria:
1 - Academic record (50%)
2 - Experience in the domain of operating systems (50%)
The jury may also decide not to assign the scholarship, if none of candidates meets the required conditions.
Work Location(s)
- Number of offers available
- 1
- Company/Institute
- INESC ID
- Country
- Portugal
- State/Province
- Lisbon
- City
- Lisbon
- Postal Code
- 1000-029
- Street
- Rua Alves Redol, 9
- Geofield
Where to apply
- rh@inesc-id.pt
Contact
- State/Province
- Lisboa
- City
- Lisboa
- Website
- Street
- Rua Alves Redol, 9
- Postal Code
- 1000-029
- rh@inesc-id.pt