13 Mar 2024
Job Information
- Organisation/Company
- Cadence EMEA
- Research Field
- Computer science » Other
- Researcher Profile
- Established Researcher (R3)
- Country
- Germany
- Application Deadline
- Type of Contract
- To be defined
- Job Status
- Negotiable
- Is the job funded through the EU Research Framework Programme?
- Not funded by an EU programme
- Is the Job related to staff position within a Research Infrastructure?
- No
Offer Description
Job Overview:
The Cadence Serdes PHY team based at our R&D center of excellence in Cork, is seeking ambitious analog designers who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm ).
The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).
The Senior Principal Analog Design Engineer will take a Technical Leadership role on the PMA design team as part of a SERDES Product Team.
Requirements
Additional Information
- Website for additional job details
Work Location(s)
- Number of offers available
- 1
- Company/Institute
- Cadence EMEA
- Country
- Ireland
- City
- Cork
- Geofield
Where to apply
- Website
Contact
- City
- Several locations in Germany, France, Italy, Israel, Sweden, UK
- Website
- woodsb@cadence.com