While artificial intelligence (AI) and machine learning techniques enjoy sustained interest across a broad range of application domains, current digital computing hardware is known to be inadequate to effectively implement AI, particularly in terms of energy efficiency. New technological breakthroughs in computational substrates are needed to enable the next AI revolutions with new forms of AI adapted to these technologies. Vertical gate-all-around nanowire field effect transistors (VNWFETs) currently under development allow a truly 3D layout configuration to continue to scale gate length and benefit from scaling improvements to energy-efficiency.
The main objective of this work is to develop a versatile 3D logic neural network compute cube (N2 C2 ) hardware including reconfigurable and non-volatile functionality. This will be a natural building block in regular 3D matrices operating through a scalable inter-cube interconnect framework structured in the x,y,z planes to develop powerful reconfigurable and energyefficient data processing engines. This radically novel hardware architecture will be capable of efficiently handling many complex tasks such as natural language processing, object recognition in images/videos, autonomous driving etc. The work will leverage the local non-volatile storage of bias and weights, massively parallel 3D processing data-paths, hardware acceleration of convolution, rectification, and activation to overcome both compute and memory walls while drastically reducing energy consumption, leading to significant performance gains compared to general-purpose architectures with hardware accelerators.
In the framework of a European research project (H2020 FVLLMONTI) and with research and industrial partners across Europe, the Heterogeneous Systems Design group at INL aims to research novel 3D compute cubes for AI based on stacked VNWFETs to explore high-performance and energy-efficient computing paradigms. In this context we are currently looking for a (m/f) PhD student for a 3 year contract.
This thesis will aim to design, implement and evaluate a novel high-performance, energy-efficient, low-footprint reconfigurable neural network compute cube based on VNWFETs. The work will involve the development of a 3D standard cell library based on conventional logic, pass-transistor logic and non-volatile logic design styles, which will then be used to build a 3D compute cube capable of carrying out element-wise non-volatile matrix multiplication, accumulation and activation through a non-linear function.
Through close collaboration with and multiple visits to the other consortium partners, the work will contribute to integrating the VNWFET device model developed by IMS (France) and GTS (Austria) into a circuit-level design flow, to generating the physical design of hardware demonstrators to be implemented by LAAS (France) and NaMLab (Germany), and to designing a complete 3D AI accelerator architecture with EPFL (Switzerland). The work will involve novel low-power logic circuit and architecture design, system-level evaluation of architectures and benchmarks and experimental measurement.
As a member of a team set up to work on this topic with the support of several sources of funding at national and European level, you will also be expected to supervise MSc students.
You have or are about to obtain an MSc in Electronic Engineering / Computer Science and have studied closely at least one of the following areas: digital integrated circuit design, multi-disciplinary or system-level modelling. Knowledge of Cadence, Verilog, SystemC is a plus. Fluency in French is also a plus but is not mandatory.
INL is a 250-strong research institute based in Lyon, France, carrying out fundamental and applied research in electronics, semiconductor materials, photonics and biotechnologies. The Heterogeneous Systems Design group is a leader in the area of advanced nanoelectronic design, with research projects and collaborations at both national and European level. Recent highlights include the development of high-performance design strategies for complex 3D integrated circuits, logic in memory using ferroelectric devices and silicon photonic networks on chip.
Send CV and statement of purpose (in English or French) to
Ian O'Connor, INL – Lyon Institute of Nanotechnology
Ecole Centrale Lyon
Tel: +33 472 186054