RESEARCH FIELDComputer science › Computer architecture
RESEARCHER PROFILEFirst Stage Researcher (R1)
APPLICATION DEADLINE31/07/2022 00:00 - Europe/Brussels
LOCATIONGermany › Duisburg
TYPE OF CONTRACTTo be defined
- In charge of whole implementation process of the first SiPearl / EPI chip from gate-level to GDS, including part of the design signoff in RTL format
- Work together with 3rd ASIC service in the first project, while building the team according to the plan
- Will lead the Digital Implementation team
This job may need small trips to our other R&D sites (Paris, Grenoble, Sophia-Antipolis).
Fluent in English to consolidate our growth and be part of the one the newest and hottest tech adventure in Europe.
Job can be based in Paris area, Maisons-Laffitte (78) or Saclay (91), Grenoble or Sophia-Antipolis (France).
You are or you have:
- 5 years of chip implementation experience, from gate-level to GDS2
- 3 years of chip integration experience, including RTL design, integration, synthesize and verification
- Experience of signoff >1 chip product designs successfully
- Senior experience in using Synopsys implementation tools
- Experience in using Mentor and Synopsys physical verification tools
- Experience in high performance chip
You are motivated by an experience within an industrial startup with fast growth and high visibility, having access to top notch silicon technology (beyond 7nm), all under a very competitive international environment.
To be defined depending on experience.
EURAXESS offer ID: 655629
Posting organisation offer ID: 12433
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