16/10/2020

VLSI System Engineer

This job offer has closed


  • ORGANISATION/COMPANY
    Universitat de Barcelona
  • RESEARCH FIELD
    Computer science
    Engineering
  • RESEARCHER PROFILE
    First Stage Researcher (R1)
  • APPLICATION DEADLINE
    15/11/2020 00:00 - Europe/Athens
  • LOCATION
    Spain › Barcelona
  • TYPE OF CONTRACT
    Temporary
  • JOB STATUS
    Full-time
  • HOURS PER WEEK
    37.5
  • OFFER STARTING DATE
    16/11/2020
  • EU RESEARCH FRAMEWORK PROGRAMME
    H2020

OFFER DESCRIPTION

We offer one position for a student in Mixed-signal VLSI designer and microsystem integration.

The core idea of this project is to produce an ASIC to control, drive, measure and communicate the project sensors. The development combines accurate analog control and measurement, wireless communications and strong low-power requirements.

The person will be dedicated to

  • Contact with the foundry for the selected process
  • Analog, digital and mixed-signal design of the ASIC/s
  • Integration of the ASIC with off-the-shelf components and the sensor
  • Support in integrated wireless communications

Experience is required managing all the EDA tools of Cadence, including schematics, simulation, layout and verification. Programming of FPGA could be necessary for the testing of the device.

 

Acronym

FOXES (H2020-FET Proactive contract 951774)

Fons

Project title

Fully Oxide-based Zero-Emission and Portable Energy Supply

IP

Juan Daniel Prades

Department

Departament d'Enginyeria Electrònica i Biomèdica

 

Gross salary per year 16.800€

Required documents

Application letter, Curriculum vitae.

Send your application to:

email

dprades@ub.edu

Name

J. Daniel Prades

email subject

FOXES VLSI System Engineer

 

More Information

Eligibility criteria

Based on experience, personal as well as professional interest

Selection process

CV, Interview, possible examination

Offer Requirements

  • REQUIRED EDUCATION LEVEL
    Engineering: Bachelor Degree or equivalent
    Computer science: Master Degree or equivalent
  • REQUIRED LANGUAGES
    ENGLISH: Good

Skills/Qualifications

Student of Electronic Engineering or similar

 

Specific Requirements

Experience in full custom design with the Cadence tools

Experience in semi-custom design and FPGA programming

Experience designing PCBs

Experience in Python programming

Map Information

Job Work Location Personal Assistance locations
Work location(s)
1 position(s) available at
Universitat de Barcelona
Spain
Barcelona
Barcelona
08028
C/Martí Franques, 1

Open, Transparent, Merit based Recruitment procedures of Researchers (OTM-R)

Know more about it at Universitat de Barcelona

Know more about OTM-R

EURAXESS offer ID: 568501

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