ORGANISATION/COMPANYUniversitat de Barcelona
RESEARCH FIELDComputer scienceEngineering
RESEARCHER PROFILEFirst Stage Researcher (R1)
APPLICATION DEADLINE15/11/2020 00:00 - Europe/Athens
LOCATIONSpain › Barcelona
TYPE OF CONTRACTTemporary
HOURS PER WEEK37.5
OFFER STARTING DATE16/11/2020
EU RESEARCH FRAMEWORK PROGRAMMEH2020
We offer one position for a student in Mixed-signal VLSI designer and microsystem integration.
The core idea of this project is to produce an ASIC to control, drive, measure and communicate the project sensors. The development combines accurate analog control and measurement, wireless communications and strong low-power requirements.
The person will be dedicated to
- Contact with the foundry for the selected process
- Analog, digital and mixed-signal design of the ASIC/s
- Integration of the ASIC with off-the-shelf components and the sensor
- Support in integrated wireless communications
Experience is required managing all the EDA tools of Cadence, including schematics, simulation, layout and verification. Programming of FPGA could be necessary for the testing of the device.
FOXES (H2020-FET Proactive contract 951774)
Fully Oxide-based Zero-Emission and Portable Energy Supply
Juan Daniel Prades
Departament d'Enginyeria Electrònica i Biomèdica
Gross salary per year 16.800€
Application letter, Curriculum vitae.
Send your application to:
J. Daniel Prades
FOXES VLSI System Engineer
Based on experience, personal as well as professional interest
CV, Interview, possible examination
REQUIRED EDUCATION LEVELEngineering: Bachelor Degree or equivalentComputer science: Master Degree or equivalent
REQUIRED LANGUAGESENGLISH: Good
Student of Electronic Engineering or similar
Experience in full custom design with the Cadence tools
Experience in semi-custom design and FPGA programming
Experience designing PCBs
Experience in Python programming
EURAXESS offer ID: 568501
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