RESEARCH FIELDComputer science › Computer architecture
RESEARCHER PROFILEFirst Stage Researcher (R1)
APPLICATION DEADLINE31/10/2019 00:00 - Europe/Brussels
LOCATIONUnited Kingdom › Bristol
TYPE OF CONTRACTTo be defined
Graphcore has created a completely new processor, the Intelligence Processing Unit (IPU), specifically designed for artificial intelligence. The IPU’s unique architecture means developers can run current machine learning models orders of magnitude faster. More importantly, it lets AI researchers undertake entirely new types of work, not possible using current technologies, to drive the next great breakthroughs in general machine intelligence.
We are looking for a DFT Engineer to join our Silicon team. Ideally the right candidate will have a strong focus on quality, an understanding of the importance of production test on the success of a product and some hands-on experience in one or more of the following areas: RTL design, simulations and debugging, synthesis, STA and DFT.
We also welcome recent/new graduates to apply for this role and work alongside our DFT leads, provided they have an interest in IC manufacture and production and are very keen and enthusiastic to learn and develop skills across all aspects of IC design/verification/manufacture.
- Working with silicon team to define DFT specifications and chip test interface
- Developing and implementing DFT architecture
- Implementing DFT infrastructure
- Working with silicon team to verify DFT features and implement design changes
- Generating structural test vectors, analyzing and improving coverage
- Working with 3rd party IPs to integrate the provided design into the DFT infrastructure
- Working with test engineers to bring up test vectors on Silicon
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
- Experience on developing DFT specifications and driving DFT architecture and methods for designs
- Solid understanding of design verification methodologies for validating DFT implementation in simulation pre-silicon
- Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues
- Experience with STA constraints development and analysis for DFT modes and SDF simulations
- Experience in silicon bring-up, debug, and validation of DFT features
- A very good knowledge of Digital Integrated Circuits and Systems
- Familiarity with programming languages such as C/C++ and Tcl/Python scripting
- Great team working and communication skills
- Degree level qualifications in Electronics or a related field
We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know.
Please note, we are only considering candidates who have an established right to work in the UK for roles based in Bristol, UK.
EURAXESS offer ID: 424623
Posting organisation offer ID: 10778
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